1. Technical Field
The present disclosure relates to a technology of distributing bus traffic of a system-on-chip using a low-power processor.
2. Description of the Related Art
The information disclosed in this section is only for understanding the background of the invention and therefore it may contain information that does not form the prior art.
A system-on-chip (SoC) is formed by embodying various functional components as one chip. The SoC includes a digital circuit. The digital circuit uses 0 (low) or 1 (high) indicating a logical value that is embodied by generating an electrical pulse. In addition, various components may have different processing speeds. In order to appropriately operate the digital circuit, electrical pulses of various components need to be synchronized. To this end, a generating period of a clock pulse or a clock frequency is used. Each component is operated based on each clock frequency. In addition, an operation of each component is synchronized according to one clock frequency.
FIG. 1 is a schematic block diagram of a general bus system of a SoC. Various components are broadly classified into a master and a slave. Referring to FIG. 1, the bus system may include a master 110, a slave 120, an arbiter 130, and a decoder 140.
The master 110 may be a device that transmits a control signal, an address, data, and so on to the slave 120 and permits the slave 120 to perform an operation such as read and write. The slave 120 may be a device that has an address area and performs read, write, etc. on the address area. The slave 120 may transmit a signal indicating a state of the slave 120 to the master 110. To this end, the master 110 may recognize the state of the slave 120. Then, the master 110 may command the slave 120 to perform a next operation.
The arbiter 130 may be a device that selects one master 110 among a plurality of masters 110. This is because two or more masters are not capable of simultaneously reading or writing in one slave. Accordingly, priority of an order in which two or more masters access one slave needs to be determined.
The decoder 140 is a device that selects an appropriate slave 120 using an address signal received from the master 110. In order to select a slave, the decoder 140 may use the received address. The address may be configured with bits. An address may be determined using some bits.
A path for transmitting a control signal, an address, data, or the like between the master 110 and the slave 120 is needed. A bus functions as the path.
FIG. 2 is a block diagram illustrating a master, a slave, and a bus of a SoC.
As illustrated in FIG. 2, a general bus system of a SoC may include a plurality of masters and a plurality of slaves. The bus system includes a plurality of master ports 230 to 233, a plurality of slave ports 240 to 243, a bus 205 for connection therebetween, a plurality of masters 210 to 213 connected to the plurality of master ports, respectively, and a plurality of slaves 220 to 223 connected to the plurality of slave ports, respectively.
The bus 205 is operated based on a bus clock frequency. In general, the bus clock frequency is set as one master clock frequency. For example, a bus clock may be set as a reference of a clock of a CPU.
The main reason for degrading performance of a product with a CPU embedded therein is the bottleneck phenomenon of bus traffic. In particular, the bottleneck phenomenon of bus traffic mainly occurs in a memory controller for access to a main memory.
To overcome this, a method of enhancing a bus clock frequency and a method of expanding a bus bandwidth is used. In the method of enhancing the bus clock frequency, a problem occurs in that power consumption of an entire system is increased. This is because that power consumption is proportional to frequency. A SoC mainly uses a low-power processor and, in this regard, power consumption is inevitably increased when a bus clock is matched with a CPU clock. The method of expanding a bus bandwidth has a limit in terms of hardware design and configuration.